Vincent Lannurien
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The two special_issues entries were proof-of-concept data and could not be corroborated: no TPDS "Edge AI Systems" or open FGCS "Serverless Computing at the Edge" call is findable, and both named real researchers as guest editors. Removed rather than corrected — nothing verifiable exists to replace them with. No open special issue was found at any tracked journal, so the field stays absent until a real CFP appears. Audited the rest of the data while there. All 39 candidate pools come from DBLP and all 471 digested papers reconcile against them, so the paper set is sound. Three defects surfaced: - DBLP returns HTML-escaped text and fetch_papers never decoded it, so 136 entities sat in the cached pools and "Theodore Y. Ts'o" reached the published ATC-2024 digest. Decoded at the fetch boundary and cleaned the existing files through the YAML parser. - SC event_dates recorded the exhibition window (Nov 17-19) instead of the conference (Nov 15-20); EuroSys ran a day long (Apr 19-24 vs 19-23). Both verified against the official sites, which also confirm every SC, EuroSys and OSDI submission deadline is exact. - TC-2025 digest carried a paraphrased title, now matching DBLP. EuroSys only records its spring cycle; the fall cycle has no home in the one-deadline-per-venue schema. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
133 lines
6.4 KiB
Markdown
133 lines
6.4 KiB
Markdown
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title: TC 2025 Digest
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venue: TC
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year: 2025
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date: '2025-01-01'
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tags: []
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paper_count: 12
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draft: false
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---
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12 papers selected.
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---
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### RV-CURE: A RISC-V Capability Architecture for Full Memory Safety
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*Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee *et al.**
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**TL;DR** — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.
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**Why notable** — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems.
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### DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation
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*Haitao Du, Yuxuan Yang 0009, Song Chen 0001, Yi Kang*
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**TL;DR** — Proposes an in-DRAM cache that isolates frequently accessed rows, preventing RowHammer hammering without costly refresh storms or off-chip overhead.
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**Why notable** — Addresses the escalating RowHammer threat directly inside DRAM with negligible performance overhead, making it a compelling candidate for near-term hardware adoption.
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### SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation
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*Wontak Han, Hyunjun Cho, Donghyuk Kim, Joo-Young Kim 0001*
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**TL;DR** — Implements subarray-level PIM with lookup-table interpolation inside DRAM to accelerate the memory-bound non-linear operations of transformer inference.
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**Why notable** — Shows how fine-grained PIM design can unblock the bottlenecks specific to LLM inference, providing a pathway to in-memory acceleration of attention and activation layers.
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### FlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization
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*Guohao Dai 0001, Ke Hong, Qiuli Mao, Xiuhong Li *et al.**
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**TL;DR** — Extends FlashDecoding with memory and latency optimizations to significantly raise GPU throughput during the autoregressive generation phase of large language models.
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**Why notable** — Directly advances the state of the art in LLM serving efficiency on GPU clusters, a problem with immediate commercial relevance.
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### Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation
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*Jordi Fornt, Enrico Reggiani, Pau Fontova-Musté, Narcís Rodas *et al.**
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**TL;DR** — Adds lightweight ISA extensions to a RISC-V CPU for mixed-precision inference via binary segmentation, avoiding heavyweight SIMD or dedicated accelerators.
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**Why notable** — Provides a cost-effective route to on-device DNN inference on RISC-V embedded cores without the area overhead of a full vector or matrix unit.
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---
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### Optimizing the Deployment of Tiny Transformers on Low-Power MCUs
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*Victor Jean-Baptiste Jung, Alessio Burrello, Moritz Scherer 0001, Francesco Conti 0001 *et al.**
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**TL;DR** — Develops an automated deployment pipeline for transformer models on microcontrollers, exploiting tiling, quantization, and kernel fusion to fit within tight memory and compute budgets.
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**Why notable** — Enables state-of-the-art sequence models to run on ultra-low-power embedded processors, bridging the gap between transformer research and IoT hardware constraints.
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---
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### Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design
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*Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li *et al.**
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**TL;DR** — Systematically studies control-flow support in dataflow/spatial accelerators and proposes a general control-flow plane abstraction that unifies existing ad hoc designs.
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**Why notable** — Offers a principled framework for architects designing the next generation of programmable spatial accelerators, where irregular control flow remains a fundamental challenge.
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### High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
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*Yijun Cui, Junjie Zhong, Bei Wang 0013, Tianyu Xu 0002 *et al.**
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**TL;DR** — Presents an optimized ASIC accelerator for CRYSTALS-Dilithium digital signatures using an improved multi-delay commutator NTT to maximize throughput.
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**Why notable** — Delivers high-performance hardware for a NIST-standardized post-quantum signature scheme, essential for quantum-safe authentication in future systems.
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### Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping
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*Yingxue Gao, Teng Wang, Lei Gong 0003, Chao Wang 0003 *et al.**
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**TL;DR** — Designs a heterogeneous accelerator for Vision Transformers that adaptively maps attention and FFN computations onto specialized dataflow engines to maximize utilization.
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**Why notable** — Addresses the heterogeneous computational demands of ViT workloads with a flexible architecture, demonstrating state-of-the-art throughput-per-watt on image recognition tasks.
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### 29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer
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*Xun Wang 0010, Xiangyu Meng 0005, Zhuoqiang Guo, Mingzhen Li 0001 *et al.**
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**TL;DR** — Scales a machine-learning-based molecular dynamics simulation to 29 billion atoms at ab-initio accuracy across 35 million cores on the Sunway supercomputer.
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**Why notable** — Sets a landmark in scientific HPC scalability, demonstrating how deep co-design of architecture, communication, and ML models enables quantum-accurate simulation at unprecedented scale.
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### AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
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*Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas *et al.**
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**TL;DR** — Introduces an open-source AXI interconnect module that enforces bandwidth and latency isolation between mixed-criticality components in heterogeneous SoCs.
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**Why notable** — Provides a practical, standards-compliant hardware mechanism for achieving real-time guarantees in safety-critical SoCs built from commodity IP blocks.
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### Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
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*Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand *et al.**
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**TL;DR** — Presents a framework for exploring the design space of layer-fused DNN execution across heterogeneous arrays, jointly optimizing tiling, scheduling, and memory allocation.
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**Why notable** — Enables systematic co-design of DNN models and heterogeneous accelerators, a key capability as networks grow more complex and hardware resources more diverse.
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