152 lines
7.4 KiB
YAML
152 lines
7.4 KiB
YAML
venue: TC
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year: 2025
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selected:
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- title: "RV-CURE: A RISC-V Capability Architecture for Full Memory Safety"
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authors:
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- Yonghae Kim
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- Anurag Kar
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- Jaewon Lee
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- Jaekyu Lee
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- Hyesoon Kim
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tldr: "Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack."
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why_notable: "Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems."
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- title: "DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation"
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authors:
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- Haitao Du
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- Yuxuan Yang 0009
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- Song Chen 0001
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- Yi Kang
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tldr: "Proposes an in-DRAM cache that isolates frequently accessed rows, preventing RowHammer hammering without costly refresh storms or off-chip overhead."
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why_notable: "Addresses the escalating RowHammer threat directly inside DRAM with negligible performance overhead, making it a compelling candidate for near-term hardware adoption."
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- title: "SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation"
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authors:
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- Wontak Han
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- Hyunjun Cho
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- Donghyuk Kim
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- Joo-Young Kim 0001
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tldr: "Implements subarray-level PIM with lookup-table interpolation inside DRAM to accelerate the memory-bound non-linear operations of transformer inference."
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why_notable: "Shows how fine-grained PIM design can unblock the bottlenecks specific to LLM inference, providing a pathway to in-memory acceleration of attention and activation layers."
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- title: "FlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization"
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authors:
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- Guohao Dai 0001
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- Ke Hong
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- Qiuli Mao
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- Xiuhong Li
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- Jiaming Xu
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- Haofeng Huang
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- Hongtu Xia
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- Xuefei Ning
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- Shengen Yan
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- Yun Liang 0001
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- Yu Wang 0002
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tldr: "Extends FlashDecoding with memory and latency optimizations to significantly raise GPU throughput during the autoregressive generation phase of large language models."
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why_notable: "Directly advances the state of the art in LLM serving efficiency on GPU clusters, a problem with immediate commercial relevance."
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- title: "Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation"
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authors:
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- Jordi Fornt
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- Enrico Reggiani
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- Pau Fontova-Musté
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- Narcís Rodas
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- Alessandro Pappalardo
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- Osman Sabri Unsal
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- Adrián Cristal Kestelman
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- Josep Altet
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- Francesc Moll
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- Jaume Abella 0001
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tldr: "Adds lightweight ISA extensions to a RISC-V CPU for mixed-precision inference via binary segmentation, avoiding heavyweight SIMD or dedicated accelerators."
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why_notable: "Provides a cost-effective route to on-device DNN inference on RISC-V embedded cores without the area overhead of a full vector or matrix unit."
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- title: "Optimizing Tiny Transformers on Low-Power MCUs"
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authors:
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- Victor Jean-Baptiste Jung
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- Alessio Burrello
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- Moritz Scherer 0001
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- Francesco Conti 0001
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- Luca Benini
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tldr: "Develops an automated deployment pipeline for transformer models on microcontrollers, exploiting tiling, quantization, and kernel fusion to fit within tight memory and compute budgets."
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why_notable: "Enables state-of-the-art sequence models to run on ultra-low-power embedded processors, bridging the gap between transformer research and IoT hardware constraints."
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- title: "Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design"
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authors:
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- Jinyi Deng
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- Xinru Tang
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- Jiahao Zhang
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- Yuxuan Li
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- Linyun Zhang
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- Fengbin Tu
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- Shaojun Wei
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- Yang Hu 0001
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- Shouyi Yin
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tldr: "Systematically studies control-flow support in dataflow/spatial accelerators and proposes a general control-flow plane abstraction that unifies existing ad hoc designs."
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why_notable: "Offers a principled framework for architects designing the next generation of programmable spatial accelerators, where irregular control flow remains a fundamental challenge."
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- title: "High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT"
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authors:
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- Yijun Cui
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- Junjie Zhong
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- Bei Wang 0013
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- Tianyu Xu 0002
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- Chenghua Wang
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- Weiqiang Liu 0001
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tldr: "Presents an optimized ASIC accelerator for CRYSTALS-Dilithium digital signatures using an improved multi-delay commutator NTT to maximize throughput."
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why_notable: "Delivers high-performance hardware for a NIST-standardized post-quantum signature scheme, essential for quantum-safe authentication in future systems."
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- title: "Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping"
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authors:
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- Yingxue Gao
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- Teng Wang
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- Lei Gong 0003
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- Chao Wang 0003
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- Dong Dai 0001
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- Yang Yang 0080
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- Xianglan Chen
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- Xi Li 0003
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- Xuehai Zhou
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tldr: "Designs a heterogeneous accelerator for Vision Transformers that adaptively maps attention and FFN computations onto specialized dataflow engines to maximize utilization."
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why_notable: "Addresses the heterogeneous computational demands of ViT workloads with a flexible architecture, demonstrating state-of-the-art throughput-per-watt on image recognition tasks."
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- title: "29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer"
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authors:
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- Xun Wang 0010
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- Xiangyu Meng 0005
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- Zhuoqiang Guo
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- Mingzhen Li 0001
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- Lijun Liu
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- Mingfan Li
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- Qian Xiao
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- Tong Zhao
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- Ninghui Sun
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- Guangming Tan
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- Weile Jia
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tldr: "Scales a machine-learning-based molecular dynamics simulation to 29 billion atoms at ab-initio accuracy across 35 million cores on the Sunway supercomputer."
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why_notable: "Sets a landmark in scientific HPC scalability, demonstrating how deep co-design of architecture, communication, and ML models enables quantum-accurate simulation at unprecedented scale."
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- title: "AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems"
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authors:
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- Thomas Benz
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- Alessandro Ottaviano
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- Chaoqun Liang
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- Robert Balas
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- Angelo Garofalo
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- Francesco Restuccia 0002
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- Alessandro Biondi 0001
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- Davide Rossi 0001
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- Luca Benini
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tldr: "Introduces an open-source AXI interconnect module that enforces bandwidth and latency isolation between mixed-criticality components in heterogeneous SoCs."
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why_notable: "Provides a practical, standards-compliant hardware mechanism for achieving real-time guarantees in safety-critical SoCs built from commodity IP blocks."
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- title: "Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators"
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authors:
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- Arne Symons
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- Linyan Mei
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- Steven Colleman
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- Pouya Houshmand
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- Sebastian Karl
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- Marian Verhelst
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tldr: "Presents a framework for exploring the design space of layer-fused DNN execution across heterogeneous arrays, jointly optimizing tiling, scheduling, and memory allocation."
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why_notable: "Enables systematic co-design of DNN models and heterogeneous accelerators, a key capability as networks grow more complex and hardware resources more diverse."
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