24 lines
31 KiB
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24 lines
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<!doctype html><html lang=en dir=auto data-theme=auto><head><meta charset=utf-8><meta http-equiv=X-UA-Compatible content="IE=edge"><meta name=viewport content="width=device-width,initial-scale=1,shrink-to-fit=no"><meta name=robots content="index, follow"><title>IPDPS 2025 Digest | Publish Assistant</title><meta name=keywords content="parallel-computing,hpc,distributed-systems,gpu"><meta name=description content="12 papers selected.
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Enhancing OmpSs-2 Suspendable Tasks by Combining Operating System and User-Level Threads with C++ Coroutines
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Arnau Cinca, Aleix Roca, Kevin Sala, Raúl Peñacoba Veigas et al.
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TL;DR — Extends the OmpSs-2 task-based runtime with C++ coroutines to implement suspendable tasks that can yield while blocked on I/O or communication without stalling the OS thread.
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Why notable — Suspendable tasks are a key missing primitive for overlapping computation and communication in task-graph runtimes; the hybrid OS/user-level thread design avoids the overhead of full context switches while remaining portable, with broad implications for OpenMP-style programming on modern heterogeneous nodes."><meta name=author content="Publish Assistant"><link rel=canonical href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/ipdps-2025/><link crossorigin=anonymous href=/vincent/publish-assistant/assets/css/stylesheet.d72f07832e13c592b3edba91680bfe70f01daac396179bcace0ac36e8e0494c6.css integrity="sha256-1y8Hgy4TxZKz7bqRaAv+cPAdqsOWF5vKzgrDbo4ElMY=" rel="preload stylesheet" as=style><link rel=icon href=https://pub.sqrt.fr/vincent/publish-assistant/favicon.ico><link rel=icon type=image/png sizes=16x16 href=https://pub.sqrt.fr/vincent/publish-assistant/favicon-16x16.png><link rel=icon type=image/png sizes=32x32 href=https://pub.sqrt.fr/vincent/publish-assistant/favicon-32x32.png><link rel=apple-touch-icon href=https://pub.sqrt.fr/vincent/publish-assistant/apple-touch-icon.png><link rel=mask-icon href=https://pub.sqrt.fr/vincent/publish-assistant/safari-pinned-tab.svg><meta name=theme-color content="#2e2e33"><meta name=msapplication-TileColor content="#2e2e33"><link rel=alternate hreflang=en href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/ipdps-2025/><noscript><style>#theme-toggle,.top-link{display:none}</style><style>@media(prefers-color-scheme:dark){:root{--theme:rgb(29, 30, 32);--entry:rgb(46, 46, 51);--primary:rgb(218, 218, 219);--secondary:rgb(155, 156, 157);--tertiary:rgb(65, 66, 68);--content:rgb(196, 196, 197);--code-block-bg:rgb(46, 46, 51);--code-bg:rgb(55, 56, 62);--border:rgb(51, 51, 51);color-scheme:dark}.list{background:var(--theme)}.toc{background:var(--entry)}}</style></noscript><script>localStorage.getItem("pref-theme")==="dark"?document.querySelector("html").dataset.theme="dark":localStorage.getItem("pref-theme")==="light"?document.querySelector("html").dataset.theme="light":window.matchMedia("(prefers-color-scheme: dark)").matches?document.querySelector("html").dataset.theme="dark":document.querySelector("html").dataset.theme="light"</script><meta property="og:url" content="https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/ipdps-2025/"><meta property="og:site_name" content="Publish Assistant"><meta property="og:title" content="IPDPS 2025 Digest"><meta property="og:description" content="12 papers selected.
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Enhancing OmpSs-2 Suspendable Tasks by Combining Operating System and User-Level Threads with C++ Coroutines Arnau Cinca, Aleix Roca, Kevin Sala, Raúl Peñacoba Veigas et al.
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TL;DR — Extends the OmpSs-2 task-based runtime with C++ coroutines to implement suspendable tasks that can yield while blocked on I/O or communication without stalling the OS thread.
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Why notable — Suspendable tasks are a key missing primitive for overlapping computation and communication in task-graph runtimes; the hybrid OS/user-level thread design avoids the overhead of full context switches while remaining portable, with broad implications for OpenMP-style programming on modern heterogeneous nodes."><meta property="og:locale" content="en_us"><meta property="og:type" content="article"><meta property="article:section" content="cloud-edge"><meta property="article:published_time" content="2025-05-19T00:00:00+00:00"><meta property="article:modified_time" content="2025-05-19T00:00:00+00:00"><meta property="article:tag" content="Parallel-Computing"><meta property="article:tag" content="Hpc"><meta property="article:tag" content="Distributed-Systems"><meta property="article:tag" content="Gpu"><meta name=twitter:card content="summary"><meta name=twitter:title content="IPDPS 2025 Digest"><meta name=twitter:description content="12 papers selected.
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Enhancing OmpSs-2 Suspendable Tasks by Combining Operating System and User-Level Threads with C++ Coroutines Arnau Cinca, Aleix Roca, Kevin Sala, Raúl Peñacoba Veigas et al.
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TL;DR — Extends the OmpSs-2 task-based runtime with C++ coroutines to implement suspendable tasks that can yield while blocked on I/O or communication without stalling the OS thread.
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Why notable — Suspendable tasks are a key missing primitive for overlapping computation and communication in task-graph runtimes; the hybrid OS/user-level thread design avoids the overhead of full context switches while remaining portable, with broad implications for OpenMP-style programming on modern heterogeneous nodes."><script type=application/ld+json>{"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Edge and Cloud Systems","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/"},{"@type":"ListItem","position":2,"name":"Digests","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/"},{"@type":"ListItem","position":3,"name":"IPDPS 2025 Digest","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/ipdps-2025/"}]}</script><script type=application/ld+json>{"@context":"https://schema.org","@type":"BlogPosting","headline":"IPDPS 2025 Digest","name":"IPDPS 2025 Digest","description":"12 papers selected.\nEnhancing OmpSs-2 Suspendable Tasks by Combining Operating System and User-Level Threads with C++ Coroutines Arnau Cinca, Aleix Roca, Kevin Sala, Raúl Peñacoba Veigas et al.\nTL;DR — Extends the OmpSs-2 task-based runtime with C++ coroutines to implement suspendable tasks that can yield while blocked on I/O or communication without stalling the OS thread.\nWhy notable — Suspendable tasks are a key missing primitive for overlapping computation and communication in task-graph runtimes; the hybrid OS/user-level thread design avoids the overhead of full context switches while remaining portable, with broad implications for OpenMP-style programming on modern heterogeneous nodes.\n","keywords":["parallel-computing","hpc","distributed-systems","gpu"],"articleBody":"12 papers selected.\nEnhancing OmpSs-2 Suspendable Tasks by Combining Operating System and User-Level Threads with C++ Coroutines Arnau Cinca, Aleix Roca, Kevin Sala, Raúl Peñacoba Veigas et al.\nTL;DR — Extends the OmpSs-2 task-based runtime with C++ coroutines to implement suspendable tasks that can yield while blocked on I/O or communication without stalling the OS thread.\nWhy notable — Suspendable tasks are a key missing primitive for overlapping computation and communication in task-graph runtimes; the hybrid OS/user-level thread design avoids the overhead of full context switches while remaining portable, with broad implications for OpenMP-style programming on modern heterogeneous nodes.\n→ Read paper PISA: An Adversarial Approach to Comparing Task Graph Scheduling Algorithms Jared Coleman, Bhaskar Krishnamachari\nTL;DR — Introduces an adversarial instance-generation framework that automatically synthesizes task graphs that expose worst-case performance gaps between competing scheduling heuristics.\nWhy notable — Benchmark-driven comparison of DAG schedulers is notoriously biased toward whoever designed the benchmark; PISA’s adversarial synthesis provides a principled, algorithm-agnostic methodology that could become a standard evaluation tool for the task-scheduling community.\n→ Read paper Parallel Scheduling of Task Graphs with Minimal Memory Requirements Pascal Fradet, Alain Girault, Alexandre Honorat\nTL;DR — Proves tight bounds and provides scheduling algorithms for task graphs that minimize peak memory usage while preserving parallelism, targeting memory-constrained accelerators.\nWhy notable — Peak memory is increasingly the binding constraint on accelerators with fixed HBM capacity; deriving schedules that are jointly memory-optimal and parallel addresses a theoretically hard trade-off that directly impacts large-scale neural network and sparse-solver pipelines.\n→ Read paper FATHOM: Fast Attention Through Optimizing Memory Elliott Binder, Arvind Sudarsanam, Ravi Sunkavalli, Tze Meng Low\nTL;DR — Redesigns the attention kernel memory access pattern to maximize reuse across the Q, K, and V tiles, achieving significant throughput gains over FlashAttention on modern GPUs.\nWhy notable — Attention is the dominant compute bottleneck in transformer inference and training; FATHOM’s memory-centric reformulation improves on the widely deployed FlashAttention baseline and demonstrates that analytical cache-tile reasoning still yields practical gains at scale.\n→ Read paper Fast and Effective Lossy Compression on GPUs and CPUs with Guaranteed Error Bounds Alex Fallin, Noushin Azami, Sheng Di, Franck Cappello et al.\nTL;DR — Presents a portable error-bounded lossy compressor that runs natively on both GPU and CPU, delivering competitive compression ratios with strict point-wise error guarantees and low latency.\nWhy notable — Scientific simulations increasingly need in-situ compression on the same GPU that runs the simulation; providing tight error bounds alongside GPU portability bridges a critical gap between scientific fidelity requirements and storage bandwidth constraints at exascale.\n→ Read paper Phase-Based Frequency Scaling for Energy-Efficient Heterogeneous Computing Lorenzo Carpentieri, Antonio De Caro, Majid Salimi Beni, Kaijie Fan et al.\nTL;DR — Dynamically scales CPU and GPU frequencies based on detected application phases to reduce energy consumption while preserving performance on heterogeneous nodes.\nWhy notable — Energy efficiency is a first-class constraint at exascale; phase-aware DVFS that jointly controls both CPU and GPU frequencies avoids the over-provisioning inherent in static policies, with measured gains directly applicable to production HPC clusters.\n→ Read paper HiCCL: A Hierarchical Collective Communication Library Mert Hidayetoglu, Simon Garcia de Gonzalo, Elliott Slaughter, Pinku Surana et al.\nTL;DR — Implements a multi-level collective communication library that decomposes all-reduce and other collectives into hierarchical sub-collectives matched to node-local, intra-rack, and inter-rack bandwidth tiers.\nWhy notable — Flat NCCL/MPI collectives ignore the hierarchical bandwidth structure of modern GPU clusters; HiCCL’s topology-aware decomposition achieves substantial throughput improvements on large distributed training jobs and is designed to be backend-agnostic.\n→ Read paper Unified Designs of Multi-Rail-Aware MPI Allreduce and Alltoall Operations Across Diverse GPU and Interconnect Systems Chen-Chun Chen, Jinghan Yao, Lang Xu, Hari Subramoni et al.\nTL;DR — Develops unified multi-rail-aware algorithms for MPI Allreduce and Alltoall that exploit all available NIC ports simultaneously across heterogeneous interconnect systems.\nWhy notable — Multi-rail configurations are increasingly common in HPC clusters yet most MPI libraries treat them as a single logical link; this work systematically closes the performance gap and the unified design enables deployment without per-system hand-tuning.\n→ Read paper CoRD: Converged RDMA Dataplane Maksym Planeta, Jan Bierbaum, Michael Roitzsch, Hermann Härtig\nTL;DR — Proposes a converged RDMA dataplane that unifies one-sided and two-sided communication semantics over a single kernel-bypass path, reducing software overhead and improving scalability.\nWhy notable — RDMA stacks remain split between one-sided verbs and two-sided message passing, forcing application writers to choose and preventing optimal use of NIC offload capabilities; CoRD’s converged abstraction enables a new class of communication patterns at near-wire speed.\n→ Read paper FlexRLHF: A Flexible Placement and Parallelism Framework for Efficient RLHF Training Youshao Xiao, Zhenglei Zhou, Fagui Mao, Weichang Wu et al.\nTL;DR — Introduces a placement and parallelism co-optimization framework for Reinforcement Learning from Human Feedback (RLHF) training that jointly schedules the actor, critic, and reward models to maximize GPU utilization.\nWhy notable — RLHF is the dominant fine-tuning paradigm for large language models but its multi-model, heterogeneous-workload structure makes naive data/model parallelism highly inefficient; FlexRLHF’s co-placement approach delivers meaningful throughput gains and establishes a design template for future RLHF infrastructure.\n→ Read paper GuardianOMP: A Framework for Highly Productive Fault Tolerance Via OpenMP Task-Level Replication Adrian Munera, Eduardo Quiñones, Sara Royuela\nTL;DR — Adds transparent task-level redundant execution to OpenMP applications, enabling automatic detection and recovery from silent data corruption without application source changes.\nWhy notable — Silent data corruption is an escalating concern as DRAM and compute elements scale into billions of transistors; GuardianOMP’s integration at the OpenMP runtime level makes resilience accessible to the broad HPC community that already uses OpenMP without requiring manual checkpoint/restart logic.\n→ Read paper Tera-Scale Multilevel Graph Partitioning Daniel Salwasser, Daniel Seemaier, Lars Gottesbüren, Peter Sanders 0001\nTL;DR — Scales multilevel graph partitioning to trillion-edge graphs through a distributed coarsening and refinement pipeline that maintains partition quality competitive with state-of-the-art tools on billion-edge benchmarks.\nWhy notable — Graph partitioning is a prerequisite for almost every distributed graph workload; reaching the tera-scale regime with near-optimal quality is a significant algorithmic and engineering milestone that directly enables graph-parallel simulation at the largest current HPC scales.\n→ Read paper ","wordCount":"1021","inLanguage":"en","datePublished":"2025-05-19T00:00:00Z","dateModified":"2025-05-19T00:00:00Z","author":{"@type":"Person","name":"Publish Assistant"},"mainEntityOfPage":{"@type":"WebPage","@id":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/ipdps-2025/"},"publisher":{"@type":"Organization","name":"Publish Assistant","logo":{"@type":"ImageObject","url":"https://pub.sqrt.fr/vincent/publish-assistant/favicon.ico"}}}</script></head><body id=top><header class=header><nav class=header-nav><div class=logo><a href=https://pub.sqrt.fr/vincent/publish-assistant/ accesskey=h title="Publish Assistant (Alt + H)">Publish Assistant</a>
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<svg viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round" class="feather feather-chevron-right"><polyline points="9 18 15 12 9 6"/></svg></nav><h1 class="post-title entry-hint-parent">IPDPS 2025 Digest</h1><div class=post-meta><span title='2025-05-19 00:00:00 +0000 UTC'>May 19, 2025</span> · <span>Publish Assistant</span></div></header><div class="post-content md-content"><p>12 papers selected.</p><hr><h3 id=enhancing-ompss-2-suspendable-tasks-by-combining-operating-system-and-user-level-threads-with-c-coroutines>Enhancing OmpSs-2 Suspendable Tasks by Combining Operating System and User-Level Threads with C++ Coroutines<a hidden class=anchor aria-hidden=true href=#enhancing-ompss-2-suspendable-tasks-by-combining-operating-system-and-user-level-threads-with-c-coroutines>#</a></h3><p><em>Arnau Cinca, Aleix Roca, Kevin Sala, Raúl Peñacoba Veigas <em>et al.</em></em></p><p><strong>TL;DR</strong> — Extends the OmpSs-2 task-based runtime with C++ coroutines to implement suspendable tasks that can yield while blocked on I/O or communication without stalling the OS thread.</p><p><strong>Why notable</strong> — Suspendable tasks are a key missing primitive for overlapping computation and communication in task-graph runtimes; the hybrid OS/user-level thread design avoids the overhead of full context switches while remaining portable, with broad implications for OpenMP-style programming on modern heterogeneous nodes.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00015>→ Read paper</a></p><hr><h3 id=pisa-an-adversarial-approach-to-comparing-task-graph-scheduling-algorithms>PISA: An Adversarial Approach to Comparing Task Graph Scheduling Algorithms<a hidden class=anchor aria-hidden=true href=#pisa-an-adversarial-approach-to-comparing-task-graph-scheduling-algorithms>#</a></h3><p><em>Jared Coleman, Bhaskar Krishnamachari</em></p><p><strong>TL;DR</strong> — Introduces an adversarial instance-generation framework that automatically synthesizes task graphs that expose worst-case performance gaps between competing scheduling heuristics.</p><p><strong>Why notable</strong> — Benchmark-driven comparison of DAG schedulers is notoriously biased toward whoever designed the benchmark; PISA’s adversarial synthesis provides a principled, algorithm-agnostic methodology that could become a standard evaluation tool for the task-scheduling community.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00014>→ Read paper</a></p><hr><h3 id=parallel-scheduling-of-task-graphs-with-minimal-memory-requirements>Parallel Scheduling of Task Graphs with Minimal Memory Requirements<a hidden class=anchor aria-hidden=true href=#parallel-scheduling-of-task-graphs-with-minimal-memory-requirements>#</a></h3><p><em>Pascal Fradet, Alain Girault, Alexandre Honorat</em></p><p><strong>TL;DR</strong> — Proves tight bounds and provides scheduling algorithms for task graphs that minimize peak memory usage while preserving parallelism, targeting memory-constrained accelerators.</p><p><strong>Why notable</strong> — Peak memory is increasingly the binding constraint on accelerators with fixed HBM capacity; deriving schedules that are jointly memory-optimal and parallel addresses a theoretically hard trade-off that directly impacts large-scale neural network and sparse-solver pipelines.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00042>→ Read paper</a></p><hr><h3 id=fathom-fast-attention-through-optimizing-memory>FATHOM: Fast Attention Through Optimizing Memory<a hidden class=anchor aria-hidden=true href=#fathom-fast-attention-through-optimizing-memory>#</a></h3><p><em>Elliott Binder, Arvind Sudarsanam, Ravi Sunkavalli, Tze Meng Low</em></p><p><strong>TL;DR</strong> — Redesigns the attention kernel memory access pattern to maximize reuse across the Q, K, and V tiles, achieving significant throughput gains over FlashAttention on modern GPUs.</p><p><strong>Why notable</strong> — Attention is the dominant compute bottleneck in transformer inference and training; FATHOM’s memory-centric reformulation improves on the widely deployed FlashAttention baseline and demonstrates that analytical cache-tile reasoning still yields practical gains at scale.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00106>→ Read paper</a></p><hr><h3 id=fast-and-effective-lossy-compression-on-gpus-and-cpus-with-guaranteed-error-bounds>Fast and Effective Lossy Compression on GPUs and CPUs with Guaranteed Error Bounds<a hidden class=anchor aria-hidden=true href=#fast-and-effective-lossy-compression-on-gpus-and-cpus-with-guaranteed-error-bounds>#</a></h3><p><em>Alex Fallin, Noushin Azami, Sheng Di, Franck Cappello <em>et al.</em></em></p><p><strong>TL;DR</strong> — Presents a portable error-bounded lossy compressor that runs natively on both GPU and CPU, delivering competitive compression ratios with strict point-wise error guarantees and low latency.</p><p><strong>Why notable</strong> — Scientific simulations increasingly need in-situ compression on the same GPU that runs the simulation; providing tight error bounds alongside GPU portability bridges a critical gap between scientific fidelity requirements and storage bandwidth constraints at exascale.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00083>→ Read paper</a></p><hr><h3 id=phase-based-frequency-scaling-for-energy-efficient-heterogeneous-computing>Phase-Based Frequency Scaling for Energy-Efficient Heterogeneous Computing<a hidden class=anchor aria-hidden=true href=#phase-based-frequency-scaling-for-energy-efficient-heterogeneous-computing>#</a></h3><p><em>Lorenzo Carpentieri, Antonio De Caro, Majid Salimi Beni, Kaijie Fan <em>et al.</em></em></p><p><strong>TL;DR</strong> — Dynamically scales CPU and GPU frequencies based on detected application phases to reduce energy consumption while preserving performance on heterogeneous nodes.</p><p><strong>Why notable</strong> — Energy efficiency is a first-class constraint at exascale; phase-aware DVFS that jointly controls both CPU and GPU frequencies avoids the over-provisioning inherent in static policies, with measured gains directly applicable to production HPC clusters.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00078>→ Read paper</a></p><hr><h3 id=hiccl-a-hierarchical-collective-communication-library>HiCCL: A Hierarchical Collective Communication Library<a hidden class=anchor aria-hidden=true href=#hiccl-a-hierarchical-collective-communication-library>#</a></h3><p><em>Mert Hidayetoglu, Simon Garcia de Gonzalo, Elliott Slaughter, Pinku Surana <em>et al.</em></em></p><p><strong>TL;DR</strong> — Implements a multi-level collective communication library that decomposes all-reduce and other collectives into hierarchical sub-collectives matched to node-local, intra-rack, and inter-rack bandwidth tiers.</p><p><strong>Why notable</strong> — Flat NCCL/MPI collectives ignore the hierarchical bandwidth structure of modern GPU clusters; HiCCL’s topology-aware decomposition achieves substantial throughput improvements on large distributed training jobs and is designed to be backend-agnostic.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00089>→ Read paper</a></p><hr><h3 id=unified-designs-of-multi-rail-aware-mpi-allreduce-and-alltoall-operations-across-diverse-gpu-and-interconnect-systems>Unified Designs of Multi-Rail-Aware MPI Allreduce and Alltoall Operations Across Diverse GPU and Interconnect Systems<a hidden class=anchor aria-hidden=true href=#unified-designs-of-multi-rail-aware-mpi-allreduce-and-alltoall-operations-across-diverse-gpu-and-interconnect-systems>#</a></h3><p><em>Chen-Chun Chen, Jinghan Yao, Lang Xu, Hari Subramoni <em>et al.</em></em></p><p><strong>TL;DR</strong> — Develops unified multi-rail-aware algorithms for MPI Allreduce and Alltoall that exploit all available NIC ports simultaneously across heterogeneous interconnect systems.</p><p><strong>Why notable</strong> — Multi-rail configurations are increasingly common in HPC clusters yet most MPI libraries treat them as a single logical link; this work systematically closes the performance gap and the unified design enables deployment without per-system hand-tuning.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00088>→ Read paper</a></p><hr><h3 id=cord-converged-rdma-dataplane>CoRD: Converged RDMA Dataplane<a hidden class=anchor aria-hidden=true href=#cord-converged-rdma-dataplane>#</a></h3><p><em>Maksym Planeta, Jan Bierbaum, Michael Roitzsch, Hermann Härtig</em></p><p><strong>TL;DR</strong> — Proposes a converged RDMA dataplane that unifies one-sided and two-sided communication semantics over a single kernel-bypass path, reducing software overhead and improving scalability.</p><p><strong>Why notable</strong> — RDMA stacks remain split between one-sided verbs and two-sided message passing, forcing application writers to choose and preventing optimal use of NIC offload capabilities; CoRD’s converged abstraction enables a new class of communication patterns at near-wire speed.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00099>→ Read paper</a></p><hr><h3 id=flexrlhf-a-flexible-placement-and-parallelism-framework-for-efficient-rlhf-training>FlexRLHF: A Flexible Placement and Parallelism Framework for Efficient RLHF Training<a hidden class=anchor aria-hidden=true href=#flexrlhf-a-flexible-placement-and-parallelism-framework-for-efficient-rlhf-training>#</a></h3><p><em>Youshao Xiao, Zhenglei Zhou, Fagui Mao, Weichang Wu <em>et al.</em></em></p><p><strong>TL;DR</strong> — Introduces a placement and parallelism co-optimization framework for Reinforcement Learning from Human Feedback (RLHF) training that jointly schedules the actor, critic, and reward models to maximize GPU utilization.</p><p><strong>Why notable</strong> — RLHF is the dominant fine-tuning paradigm for large language models but its multi-model, heterogeneous-workload structure makes naive data/model parallelism highly inefficient; FlexRLHF’s co-placement approach delivers meaningful throughput gains and establishes a design template for future RLHF infrastructure.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00039>→ Read paper</a></p><hr><h3 id=guardianomp-a-framework-for-highly-productive-fault-tolerance-via-openmp-task-level-replication>GuardianOMP: A Framework for Highly Productive Fault Tolerance Via OpenMP Task-Level Replication<a hidden class=anchor aria-hidden=true href=#guardianomp-a-framework-for-highly-productive-fault-tolerance-via-openmp-task-level-replication>#</a></h3><p><em>Adrian Munera, Eduardo Quiñones, Sara Royuela</em></p><p><strong>TL;DR</strong> — Adds transparent task-level redundant execution to OpenMP applications, enabling automatic detection and recovery from silent data corruption without application source changes.</p><p><strong>Why notable</strong> — Silent data corruption is an escalating concern as DRAM and compute elements scale into billions of transistors; GuardianOMP’s integration at the OpenMP runtime level makes resilience accessible to the broad HPC community that already uses OpenMP without requiring manual checkpoint/restart logic.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00114>→ Read paper</a></p><hr><h3 id=tera-scale-multilevel-graph-partitioning>Tera-Scale Multilevel Graph Partitioning<a hidden class=anchor aria-hidden=true href=#tera-scale-multilevel-graph-partitioning>#</a></h3><p><em>Daniel Salwasser, Daniel Seemaier, Lars Gottesbüren, Peter Sanders 0001</em></p><p><strong>TL;DR</strong> — Scales multilevel graph partitioning to trillion-edge graphs through a distributed coarsening and refinement pipeline that maintains partition quality competitive with state-of-the-art tools on billion-edge benchmarks.</p><p><strong>Why notable</strong> — Graph partitioning is a prerequisite for almost every distributed graph workload; reaching the tera-scale regime with near-optimal quality is a significant algorithmic and engineering milestone that directly enables graph-parallel simulation at the largest current HPC scales.</p><p><a href=https://doi.org/10.1109/IPDPS64566.2025.00033>→ Read paper</a></p></div><footer class=post-footer><ul class=post-tags><li><a href=https://pub.sqrt.fr/vincent/publish-assistant/tags/parallel-computing/>Parallel-Computing</a></li><li><a href=https://pub.sqrt.fr/vincent/publish-assistant/tags/hpc/>Hpc</a></li><li><a href=https://pub.sqrt.fr/vincent/publish-assistant/tags/distributed-systems/>Distributed-Systems</a></li><li><a href=https://pub.sqrt.fr/vincent/publish-assistant/tags/gpu/>Gpu</a></li></ul><nav class=paginav><a class=prev href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/mobisys-2025/><span class=title>« Prev</span>
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