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<!doctype html><html lang=en dir=auto data-theme=auto><head><meta charset=utf-8><meta http-equiv=X-UA-Compatible content="IE=edge"><meta name=viewport content="width=device-width,initial-scale=1,shrink-to-fit=no"><meta name=robots content="index, follow"><title>TC 2025 Digest | Publish Assistant</title><meta name=keywords content><meta name=description content="12 papers selected.
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RV-CURE: A RISC-V Capability Architecture for Full Memory Safety
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Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee et al.
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TL;DR — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.
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Why notable — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems."><meta name=author content="Publish Assistant"><link rel=canonical href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2025/><link crossorigin=anonymous href=/vincent/publish-assistant/assets/css/stylesheet.d72f07832e13c592b3edba91680bfe70f01daac396179bcace0ac36e8e0494c6.css integrity="sha256-1y8Hgy4TxZKz7bqRaAv+cPAdqsOWF5vKzgrDbo4ElMY=" rel="preload stylesheet" as=style><link rel=icon href=https://pub.sqrt.fr/vincent/publish-assistant/favicon.ico><link rel=icon type=image/png sizes=16x16 href=https://pub.sqrt.fr/vincent/publish-assistant/favicon-16x16.png><link rel=icon type=image/png sizes=32x32 href=https://pub.sqrt.fr/vincent/publish-assistant/favicon-32x32.png><link rel=apple-touch-icon href=https://pub.sqrt.fr/vincent/publish-assistant/apple-touch-icon.png><link rel=mask-icon href=https://pub.sqrt.fr/vincent/publish-assistant/safari-pinned-tab.svg><meta name=theme-color content="#2e2e33"><meta name=msapplication-TileColor content="#2e2e33"><link rel=alternate hreflang=en href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2025/><noscript><style>#theme-toggle,.top-link{display:none}</style><style>@media(prefers-color-scheme:dark){:root{--theme:rgb(29, 30, 32);--entry:rgb(46, 46, 51);--primary:rgb(218, 218, 219);--secondary:rgb(155, 156, 157);--tertiary:rgb(65, 66, 68);--content:rgb(196, 196, 197);--code-block-bg:rgb(46, 46, 51);--code-bg:rgb(55, 56, 62);--border:rgb(51, 51, 51);color-scheme:dark}.list{background:var(--theme)}.toc{background:var(--entry)}}</style></noscript><script>localStorage.getItem("pref-theme")==="dark"?document.querySelector("html").dataset.theme="dark":localStorage.getItem("pref-theme")==="light"?document.querySelector("html").dataset.theme="light":window.matchMedia("(prefers-color-scheme: dark)").matches?document.querySelector("html").dataset.theme="dark":document.querySelector("html").dataset.theme="light"</script><meta property="og:url" content="https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2025/"><meta property="og:site_name" content="Publish Assistant"><meta property="og:title" content="TC 2025 Digest"><meta property="og:description" content="12 papers selected.
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RV-CURE: A RISC-V Capability Architecture for Full Memory Safety Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee et al.
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TL;DR — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.
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Why notable — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems."><meta property="og:locale" content="en_us"><meta property="og:type" content="article"><meta property="article:section" content="cloud-edge"><meta property="article:published_time" content="2025-01-01T00:00:00+00:00"><meta property="article:modified_time" content="2025-01-01T00:00:00+00:00"><meta name=twitter:card content="summary"><meta name=twitter:title content="TC 2025 Digest"><meta name=twitter:description content="12 papers selected.
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RV-CURE: A RISC-V Capability Architecture for Full Memory Safety Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee et al.
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TL;DR — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.
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Why notable — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems."><script type=application/ld+json>{"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Edge and Cloud Systems","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/"},{"@type":"ListItem","position":2,"name":"Digests","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/"},{"@type":"ListItem","position":3,"name":"TC 2025 Digest","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2025/"}]}</script><script type=application/ld+json>{"@context":"https://schema.org","@type":"BlogPosting","headline":"TC 2025 Digest","name":"TC 2025 Digest","description":"12 papers selected.\nRV-CURE: A RISC-V Capability Architecture for Full Memory Safety Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee et al.\nTL;DR — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.\nWhy notable — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems.\n","keywords":[],"articleBody":"12 papers selected.\nRV-CURE: A RISC-V Capability Architecture for Full Memory Safety Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee et al.\nTL;DR — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.\nWhy notable — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems.\nDIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation Haitao Du, Yuxuan Yang 0009, Song Chen 0001, Yi Kang\nTL;DR — Proposes an in-DRAM cache that isolates frequently accessed rows, preventing RowHammer hammering without costly refresh storms or off-chip overhead.\nWhy notable — Addresses the escalating RowHammer threat directly inside DRAM with negligible performance overhead, making it a compelling candidate for near-term hardware adoption.\nSAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation Wontak Han, Hyunjun Cho, Donghyuk Kim, Joo-Young Kim 0001\nTL;DR — Implements subarray-level PIM with lookup-table interpolation inside DRAM to accelerate the memory-bound non-linear operations of transformer inference.\nWhy notable — Shows how fine-grained PIM design can unblock the bottlenecks specific to LLM inference, providing a pathway to in-memory acceleration of attention and activation layers.\nFlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization Guohao Dai 0001, Ke Hong, Qiuli Mao, Xiuhong Li et al.\nTL;DR — Extends FlashDecoding with memory and latency optimizations to significantly raise GPU throughput during the autoregressive generation phase of large language models.\nWhy notable — Directly advances the state of the art in LLM serving efficiency on GPU clusters, a problem with immediate commercial relevance.\nMix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation Jordi Fornt, Enrico Reggiani, Pau Fontova-Musté, Narcís Rodas et al.\nTL;DR — Adds lightweight ISA extensions to a RISC-V CPU for mixed-precision inference via binary segmentation, avoiding heavyweight SIMD or dedicated accelerators.\nWhy notable — Provides a cost-effective route to on-device DNN inference on RISC-V embedded cores without the area overhead of a full vector or matrix unit.\nOptimizing the Deployment of Tiny Transformers on Low-Power MCUs Victor Jean-Baptiste Jung, Alessio Burrello, Moritz Scherer 0001, Francesco Conti 0001 et al.\nTL;DR — Develops an automated deployment pipeline for transformer models on microcontrollers, exploiting tiling, quantization, and kernel fusion to fit within tight memory and compute budgets.\nWhy notable — Enables state-of-the-art sequence models to run on ultra-low-power embedded processors, bridging the gap between transformer research and IoT hardware constraints.\nRethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li et al.\nTL;DR — Systematically studies control-flow support in dataflow/spatial accelerators and proposes a general control-flow plane abstraction that unifies existing ad hoc designs.\nWhy notable — Offers a principled framework for architects designing the next generation of programmable spatial accelerators, where irregular control flow remains a fundamental challenge.\nHigh-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT Yijun Cui, Junjie Zhong, Bei Wang 0013, Tianyu Xu 0002 et al.\nTL;DR — Presents an optimized ASIC accelerator for CRYSTALS-Dilithium digital signatures using an improved multi-delay commutator NTT to maximize throughput.\nWhy notable — Delivers high-performance hardware for a NIST-standardized post-quantum signature scheme, essential for quantum-safe authentication in future systems.\nHardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping Yingxue Gao, Teng Wang, Lei Gong 0003, Chao Wang 0003 et al.\nTL;DR — Designs a heterogeneous accelerator for Vision Transformers that adaptively maps attention and FFN computations onto specialized dataflow engines to maximize utilization.\nWhy notable — Addresses the heterogeneous computational demands of ViT workloads with a flexible architecture, demonstrating state-of-the-art throughput-per-watt on image recognition tasks.\n29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer Xun Wang 0010, Xiangyu Meng 0005, Zhuoqiang Guo, Mingzhen Li 0001 et al.\nTL;DR — Scales a machine-learning-based molecular dynamics simulation to 29 billion atoms at ab-initio accuracy across 35 million cores on the Sunway supercomputer.\nWhy notable — Sets a landmark in scientific HPC scalability, demonstrating how deep co-design of architecture, communication, and ML models enables quantum-accurate simulation at unprecedented scale.\nAXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas et al.\nTL;DR — Introduces an open-source AXI interconnect module that enforces bandwidth and latency isolation between mixed-criticality components in heterogeneous SoCs.\nWhy notable — Provides a practical, standards-compliant hardware mechanism for achieving real-time guarantees in safety-critical SoCs built from commodity IP blocks.\nStream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand et al.\nTL;DR — Presents a framework for exploring the design space of layer-fused DNN execution across heterogeneous arrays, jointly optimizing tiling, scheduling, and memory allocation.\nWhy notable — Enables systematic co-design of DNN models and heterogeneous accelerators, a key capability as networks grow more complex and hardware resources more diverse.\n","wordCount":"824","inLanguage":"en","datePublished":"2025-01-01T00:00:00Z","dateModified":"2025-01-01T00:00:00Z","author":{"@type":"Person","name":"Publish Assistant"},"mainEntityOfPage":{"@type":"WebPage","@id":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2025/"},"publisher":{"@type":"Organization","name":"Publish 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<svg viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round" class="feather feather-chevron-right"><polyline points="9 18 15 12 9 6"/></svg></nav><h1 class="post-title entry-hint-parent">TC 2025 Digest</h1><div class=post-meta><span title='2025-01-01 00:00:00 +0000 UTC'>January 1, 2025</span> · <span>Publish Assistant</span></div></header><div class="post-content md-content"><p>12 papers selected.</p><hr><h3 id=rv-cure-a-risc-v-capability-architecture-for-full-memory-safety>RV-CURE: A RISC-V Capability Architecture for Full Memory Safety<a hidden class=anchor aria-hidden=true href=#rv-cure-a-risc-v-capability-architecture-for-full-memory-safety>#</a></h3><p><em>Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee <em>et al.</em></em></p><p><strong>TL;DR</strong> — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.</p><p><strong>Why notable</strong> — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems.</p><hr><h3 id=divide-efficient-rowhammer-defense-via-in-dram-cache-based-hot-data-isolation>DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation<a hidden class=anchor aria-hidden=true href=#divide-efficient-rowhammer-defense-via-in-dram-cache-based-hot-data-isolation>#</a></h3><p><em>Haitao Du, Yuxuan Yang 0009, Song Chen 0001, Yi Kang</em></p><p><strong>TL;DR</strong> — Proposes an in-DRAM cache that isolates frequently accessed rows, preventing RowHammer hammering without costly refresh storms or off-chip overhead.</p><p><strong>Why notable</strong> — Addresses the escalating RowHammer threat directly inside DRAM with negligible performance overhead, making it a compelling candidate for near-term hardware adoption.</p><hr><h3 id=sal-pim-a-subarray-level-processing-in-memory-architecture-with-lut-based-linear-interpolation-for-transformer-based-text-generation>SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation<a hidden class=anchor aria-hidden=true href=#sal-pim-a-subarray-level-processing-in-memory-architecture-with-lut-based-linear-interpolation-for-transformer-based-text-generation>#</a></h3><p><em>Wontak Han, Hyunjun Cho, Donghyuk Kim, Joo-Young Kim 0001</em></p><p><strong>TL;DR</strong> — Implements subarray-level PIM with lookup-table interpolation inside DRAM to accelerate the memory-bound non-linear operations of transformer inference.</p><p><strong>Why notable</strong> — Shows how fine-grained PIM design can unblock the bottlenecks specific to LLM inference, providing a pathway to in-memory acceleration of attention and activation layers.</p><hr><h3 id=flashdecodingnext-high-throughput-llm-inference-with-latency-and-memory-optimization>FlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization<a hidden class=anchor aria-hidden=true href=#flashdecodingnext-high-throughput-llm-inference-with-latency-and-memory-optimization>#</a></h3><p><em>Guohao Dai 0001, Ke Hong, Qiuli Mao, Xiuhong Li <em>et al.</em></em></p><p><strong>TL;DR</strong> — Extends FlashDecoding with memory and latency optimizations to significantly raise GPU throughput during the autoregressive generation phase of large language models.</p><p><strong>Why notable</strong> — Directly advances the state of the art in LLM serving efficiency on GPU clusters, a problem with immediate commercial relevance.</p><hr><h3 id=mix-gemm-extending-risc-v-cpus-for-energy-efficient-mixed-precision-dnn-inference-using-binary-segmentation>Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation<a hidden class=anchor aria-hidden=true href=#mix-gemm-extending-risc-v-cpus-for-energy-efficient-mixed-precision-dnn-inference-using-binary-segmentation>#</a></h3><p><em>Jordi Fornt, Enrico Reggiani, Pau Fontova-Musté, Narcís Rodas <em>et al.</em></em></p><p><strong>TL;DR</strong> — Adds lightweight ISA extensions to a RISC-V CPU for mixed-precision inference via binary segmentation, avoiding heavyweight SIMD or dedicated accelerators.</p><p><strong>Why notable</strong> — Provides a cost-effective route to on-device DNN inference on RISC-V embedded cores without the area overhead of a full vector or matrix unit.</p><hr><h3 id=optimizing-the-deployment-of-tiny-transformers-on-low-power-mcus>Optimizing the Deployment of Tiny Transformers on Low-Power MCUs<a hidden class=anchor aria-hidden=true href=#optimizing-the-deployment-of-tiny-transformers-on-low-power-mcus>#</a></h3><p><em>Victor Jean-Baptiste Jung, Alessio Burrello, Moritz Scherer 0001, Francesco Conti 0001 <em>et al.</em></em></p><p><strong>TL;DR</strong> — Develops an automated deployment pipeline for transformer models on microcontrollers, exploiting tiling, quantization, and kernel fusion to fit within tight memory and compute budgets.</p><p><strong>Why notable</strong> — Enables state-of-the-art sequence models to run on ultra-low-power embedded processors, bridging the gap between transformer research and IoT hardware constraints.</p><hr><h3 id=rethinking-control-flow-in-spatial-architectures-insights-into-control-flow-plane-design>Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design<a hidden class=anchor aria-hidden=true href=#rethinking-control-flow-in-spatial-architectures-insights-into-control-flow-plane-design>#</a></h3><p><em>Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li <em>et al.</em></em></p><p><strong>TL;DR</strong> — Systematically studies control-flow support in dataflow/spatial accelerators and proposes a general control-flow plane abstraction that unifies existing ad hoc designs.</p><p><strong>Why notable</strong> — Offers a principled framework for architects designing the next generation of programmable spatial accelerators, where irregular control flow remains a fundamental challenge.</p><hr><h3 id=high-performance-hardware-implementation-of-crystals-dilithium-based-on-improved-mdc-ntt>High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT<a hidden class=anchor aria-hidden=true href=#high-performance-hardware-implementation-of-crystals-dilithium-based-on-improved-mdc-ntt>#</a></h3><p><em>Yijun Cui, Junjie Zhong, Bei Wang 0013, Tianyu Xu 0002 <em>et al.</em></em></p><p><strong>TL;DR</strong> — Presents an optimized ASIC accelerator for CRYSTALS-Dilithium digital signatures using an improved multi-delay commutator NTT to maximize throughput.</p><p><strong>Why notable</strong> — Delivers high-performance hardware for a NIST-standardized post-quantum signature scheme, essential for quantum-safe authentication in future systems.</p><hr><h3 id=hardware-accelerated-vision-transformer-via-heterogeneous-architecture-design-and-adaptive-dataflow-mapping>Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping<a hidden class=anchor aria-hidden=true href=#hardware-accelerated-vision-transformer-via-heterogeneous-architecture-design-and-adaptive-dataflow-mapping>#</a></h3><p><em>Yingxue Gao, Teng Wang, Lei Gong 0003, Chao Wang 0003 <em>et al.</em></em></p><p><strong>TL;DR</strong> — Designs a heterogeneous accelerator for Vision Transformers that adaptively maps attention and FFN computations onto specialized dataflow engines to maximize utilization.</p><p><strong>Why notable</strong> — Addresses the heterogeneous computational demands of ViT workloads with a flexible architecture, demonstrating state-of-the-art throughput-per-watt on image recognition tasks.</p><hr><h3 id=29-billion-atoms-molecular-dynamics-simulation-with-ab-initio-accuracy-on-35-million-cores-of-new-sunway-supercomputer>29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer<a hidden class=anchor aria-hidden=true href=#29-billion-atoms-molecular-dynamics-simulation-with-ab-initio-accuracy-on-35-million-cores-of-new-sunway-supercomputer>#</a></h3><p><em>Xun Wang 0010, Xiangyu Meng 0005, Zhuoqiang Guo, Mingzhen Li 0001 <em>et al.</em></em></p><p><strong>TL;DR</strong> — Scales a machine-learning-based molecular dynamics simulation to 29 billion atoms at ab-initio accuracy across 35 million cores on the Sunway supercomputer.</p><p><strong>Why notable</strong> — Sets a landmark in scientific HPC scalability, demonstrating how deep co-design of architecture, communication, and ML models enables quantum-accurate simulation at unprecedented scale.</p><hr><h3 id=axi-realm-safe-modular-and-lightweight-traffic-monitoring-and-regulation-for-heterogeneous-mixed-criticality-systems>AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems<a hidden class=anchor aria-hidden=true href=#axi-realm-safe-modular-and-lightweight-traffic-monitoring-and-regulation-for-heterogeneous-mixed-criticality-systems>#</a></h3><p><em>Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas <em>et al.</em></em></p><p><strong>TL;DR</strong> — Introduces an open-source AXI interconnect module that enforces bandwidth and latency isolation between mixed-criticality components in heterogeneous SoCs.</p><p><strong>Why notable</strong> — Provides a practical, standards-compliant hardware mechanism for achieving real-time guarantees in safety-critical SoCs built from commodity IP blocks.</p><hr><h3 id=stream-design-space-exploration-of-layer-fused-dnns-on-heterogeneous-dataflow-accelerators>Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators<a hidden class=anchor aria-hidden=true href=#stream-design-space-exploration-of-layer-fused-dnns-on-heterogeneous-dataflow-accelerators>#</a></h3><p><em>Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand <em>et al.</em></em></p><p><strong>TL;DR</strong> — Presents a framework for exploring the design space of layer-fused DNN execution across heterogeneous arrays, jointly optimizing tiling, scheduling, and memory allocation.</p><p><strong>Why notable</strong> — Enables systematic co-design of DNN models and heterogeneous accelerators, a key capability as networks grow more complex and hardware resources more diverse.</p></div><footer class=post-footer><ul class=post-tags></ul><nav class=paginav><a class=prev href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/sosp-2025/><span class=title>« Prev</span>
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