29 lines
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29 lines
25 KiB
HTML
<!doctype html><html lang=en dir=auto data-theme=auto><head><meta charset=utf-8><meta http-equiv=X-UA-Compatible content="IE=edge"><meta name=viewport content="width=device-width,initial-scale=1,shrink-to-fit=no"><meta name=robots content="index, follow"><title>TC 2024 Digest | Publish Assistant</title><meta name=keywords content><meta name=description content="12 papers selected.
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Achieving DRAM-Like PCM by Trading Off Capacity for Latency
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Irina Alam, Puneet Gupta 0001
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TL;DR — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.
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Why notable — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.
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A High-Performance, Energy-Efficient Modular DMA Engine Architecture
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Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel et al."><meta name=author content="Publish Assistant"><link rel=canonical href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2024/><link crossorigin=anonymous href=/vincent/publish-assistant/assets/css/stylesheet.d72f07832e13c592b3edba91680bfe70f01daac396179bcace0ac36e8e0494c6.css integrity="sha256-1y8Hgy4TxZKz7bqRaAv+cPAdqsOWF5vKzgrDbo4ElMY=" rel="preload stylesheet" as=style><link rel=icon href=https://pub.sqrt.fr/vincent/publish-assistant/favicon.ico><link rel=icon type=image/png sizes=16x16 href=https://pub.sqrt.fr/vincent/publish-assistant/favicon-16x16.png><link rel=icon type=image/png sizes=32x32 href=https://pub.sqrt.fr/vincent/publish-assistant/favicon-32x32.png><link rel=apple-touch-icon href=https://pub.sqrt.fr/vincent/publish-assistant/apple-touch-icon.png><link rel=mask-icon href=https://pub.sqrt.fr/vincent/publish-assistant/safari-pinned-tab.svg><meta name=theme-color content="#2e2e33"><meta name=msapplication-TileColor content="#2e2e33"><link rel=alternate hreflang=en href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2024/><noscript><style>#theme-toggle,.top-link{display:none}</style><style>@media(prefers-color-scheme:dark){:root{--theme:rgb(29, 30, 32);--entry:rgb(46, 46, 51);--primary:rgb(218, 218, 219);--secondary:rgb(155, 156, 157);--tertiary:rgb(65, 66, 68);--content:rgb(196, 196, 197);--code-block-bg:rgb(46, 46, 51);--code-bg:rgb(55, 56, 62);--border:rgb(51, 51, 51);color-scheme:dark}.list{background:var(--theme)}.toc{background:var(--entry)}}</style></noscript><script>localStorage.getItem("pref-theme")==="dark"?document.querySelector("html").dataset.theme="dark":localStorage.getItem("pref-theme")==="light"?document.querySelector("html").dataset.theme="light":window.matchMedia("(prefers-color-scheme: dark)").matches?document.querySelector("html").dataset.theme="dark":document.querySelector("html").dataset.theme="light"</script><meta property="og:url" content="https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2024/"><meta property="og:site_name" content="Publish Assistant"><meta property="og:title" content="TC 2024 Digest"><meta property="og:description" content="12 papers selected.
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Achieving DRAM-Like PCM by Trading Off Capacity for Latency Irina Alam, Puneet Gupta 0001
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TL;DR — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.
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Why notable — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.
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A High-Performance, Energy-Efficient Modular DMA Engine Architecture Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel et al."><meta property="og:locale" content="en_us"><meta property="og:type" content="article"><meta property="article:section" content="cloud-edge"><meta property="article:published_time" content="2024-01-01T00:00:00+00:00"><meta property="article:modified_time" content="2024-01-01T00:00:00+00:00"><meta name=twitter:card content="summary"><meta name=twitter:title content="TC 2024 Digest"><meta name=twitter:description content="12 papers selected.
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Achieving DRAM-Like PCM by Trading Off Capacity for Latency Irina Alam, Puneet Gupta 0001
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TL;DR — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.
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Why notable — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.
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A High-Performance, Energy-Efficient Modular DMA Engine Architecture Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel et al."><script type=application/ld+json>{"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Edge and Cloud Systems","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/"},{"@type":"ListItem","position":2,"name":"Digests","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/"},{"@type":"ListItem","position":3,"name":"TC 2024 Digest","item":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2024/"}]}</script><script type=application/ld+json>{"@context":"https://schema.org","@type":"BlogPosting","headline":"TC 2024 Digest","name":"TC 2024 Digest","description":"12 papers selected.\nAchieving DRAM-Like PCM by Trading Off Capacity for Latency Irina Alam, Puneet Gupta 0001\nTL;DR — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.\nWhy notable — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.\nA High-Performance, Energy-Efficient Modular DMA Engine Architecture Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel et al.\n","keywords":[],"articleBody":"12 papers selected.\nAchieving DRAM-Like PCM by Trading Off Capacity for Latency Irina Alam, Puneet Gupta 0001\nTL;DR — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.\nWhy notable — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.\nA High-Performance, Energy-Efficient Modular DMA Engine Architecture Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel et al.\nTL;DR — Presents a modular, parametric DMA engine design achieving high bandwidth and low energy overhead for heterogeneous SoC data movement.\nWhy notable — Provides an open, well-evaluated DMA baseline that researchers building custom SoCs or accelerators can directly reuse or benchmark against.\nSplit-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber Wenbo Guo 0009, Shuguo Li\nTL;DR — Designs a compact FPGA/ASIC hardware accelerator for the CRYSTALS-Kyber post-quantum key encapsulation mechanism using a split-radix NTT.\nWhy notable — Demonstrates efficient hardware realization of a NIST-standardized post-quantum algorithm, critical for transitioning real systems to quantum-resistant cryptography.\nAccelerating Sparse DNNs Based on Tiled GEMM Cong Guo 0003, Fengchen Xue, Jingwen Leng, Yuxian Qiu et al.\nTL;DR — Accelerates sparse deep neural network inference by restructuring sparse matrix multiplication into tiled GEMM operations that map efficiently onto GPU tensor cores.\nWhy notable — Bridges the gap between theoretical sparsity speedups and GPU hardware realities, achieving practical inference acceleration on commodity hardware.\nXvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation Eric Guthmuller, César Fuguet, Andrea Bocco, Jérôme Fereyre et al.\nTL;DR — Defines a RISC-V ISA extension supporting variable-precision floating-point operations beyond IEEE 754 standard widths, targeting HPC and scientific computing.\nWhy notable — Addresses precision flexibility at the ISA level, enabling energy-efficient mixed-precision HPC workloads without requiring separate co-processors.\nEnabling HW-Based Task Scheduling in Large Multicore Architectures Lucas Morais, Carlos Álvarez 0001, Daniel Jiménez-González, Juan Miguel De Haro Ruiz et al.\nTL;DR — Implements task-scheduling logic directly in hardware for large multicore chips, reducing OS scheduling overhead and improving parallelism exploitation.\nWhy notable — Demonstrates that offloading fine-grained task management to hardware can substantially reduce software overhead in many-core systems.\nAra2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli et al.\nTL;DR — Presents Ara2, an open-source RISC-V vector processor fully compliant with RVV 1.0, evaluated across single- and multi-lane configurations for energy-efficient vector workloads.\nWhy notable — Provides the community with a production-quality, open RVV 1.0 reference design and a thorough design-space exploration of vector-processor microarchitecture.\nEcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators Lois Orosa 0001, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos et al.\nTL;DR — Systematically analyzes and optimizes dataflow schedules for convolutional layers on low-power DNN accelerators, yielding significant energy savings.\nWhy notable — Provides a principled framework for dataflow selection that benefits embedded AI accelerator designers targeting energy-constrained deployments.\nPrefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender Luyi Li, Jiayi Huang 0001, Lang Feng 0001, Zhongfeng Wang 0001\nTL;DR — Proposes a hardware prefetching mechanism that disguises cache access patterns to defend against conflict-based cache side-channel attacks with low performance overhead.\nWhy notable — Addresses cache side-channel attacks at the microarchitecture level without relying on software mitigations, offering a lightweight and transparent defense.\nRandomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks Wei Song 0002, Zihan Xue, Jinchi Han, Zhenzhen Li et al.\nTL;DR — Introduces a cache randomization scheme for set-associative caches that eliminates conflict-based side-channel attack primitives with minimal performance overhead.\nWhy notable — Provides a strong and low-cost architectural defense against a broad class of cache timing attacks that affect nearly all modern processors.\nSCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini\nTL;DR — Proposes a framework for detecting and mitigating hardware Trojans inserted during chip fabrication using lightweight logic testing combined with side-channel verification.\nWhy notable — Tackles the increasingly critical supply-chain hardware-security threat with a practical methodology applicable during standard chip validation flows.\nGraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks Sungmin Yun 0001, Hwayong Nam, Jaehyun Park 0006, Byeongho Kim et al.\nTL;DR — Designs a near-data processing accelerator tailored for graph neural network inference, co-locating compute with graph-structured memory to cut off-chip traffic.\nWhy notable — Demonstrates that memory-wall bottlenecks in GNN inference can be alleviated by a purpose-built PIM design, achieving substantial speedup and energy efficiency gains.\n","wordCount":"748","inLanguage":"en","datePublished":"2024-01-01T00:00:00Z","dateModified":"2024-01-01T00:00:00Z","author":{"@type":"Person","name":"Publish Assistant"},"mainEntityOfPage":{"@type":"WebPage","@id":"https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/tc-2024/"},"publisher":{"@type":"Organization","name":"Publish Assistant","logo":{"@type":"ImageObject","url":"https://pub.sqrt.fr/vincent/publish-assistant/favicon.ico"}}}</script></head><body id=top><header class=header><nav class=header-nav><div class=logo><a href=https://pub.sqrt.fr/vincent/publish-assistant/ accesskey=h title="Publish Assistant (Alt + H)">Publish Assistant</a>
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<svg viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round" class="feather feather-chevron-right"><polyline points="9 18 15 12 9 6"/></svg></nav><h1 class="post-title entry-hint-parent">TC 2024 Digest</h1><div class=post-meta><span title='2024-01-01 00:00:00 +0000 UTC'>January 1, 2024</span> · <span>Publish Assistant</span></div></header><div class="post-content md-content"><p>12 papers selected.</p><hr><h3 id=achieving-dram-like-pcm-by-trading-off-capacity-for-latency>Achieving DRAM-Like PCM by Trading Off Capacity for Latency<a hidden class=anchor aria-hidden=true href=#achieving-dram-like-pcm-by-trading-off-capacity-for-latency>#</a></h3><p><em>Irina Alam, Puneet Gupta 0001</em></p><p><strong>TL;DR</strong> — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.</p><p><strong>Why notable</strong> — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.</p><hr><h3 id=a-high-performance-energy-efficient-modular-dma-engine-architecture>A High-Performance, Energy-Efficient Modular DMA Engine Architecture<a hidden class=anchor aria-hidden=true href=#a-high-performance-energy-efficient-modular-dma-engine-architecture>#</a></h3><p><em>Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel <em>et al.</em></em></p><p><strong>TL;DR</strong> — Presents a modular, parametric DMA engine design achieving high bandwidth and low energy overhead for heterogeneous SoC data movement.</p><p><strong>Why notable</strong> — Provides an open, well-evaluated DMA baseline that researchers building custom SoCs or accelerators can directly reuse or benchmark against.</p><hr><h3 id=split-radix-based-compact-hardware-architecture-for-crystals-kyber>Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber<a hidden class=anchor aria-hidden=true href=#split-radix-based-compact-hardware-architecture-for-crystals-kyber>#</a></h3><p><em>Wenbo Guo 0009, Shuguo Li</em></p><p><strong>TL;DR</strong> — Designs a compact FPGA/ASIC hardware accelerator for the CRYSTALS-Kyber post-quantum key encapsulation mechanism using a split-radix NTT.</p><p><strong>Why notable</strong> — Demonstrates efficient hardware realization of a NIST-standardized post-quantum algorithm, critical for transitioning real systems to quantum-resistant cryptography.</p><hr><h3 id=accelerating-sparse-dnns-based-on-tiled-gemm>Accelerating Sparse DNNs Based on Tiled GEMM<a hidden class=anchor aria-hidden=true href=#accelerating-sparse-dnns-based-on-tiled-gemm>#</a></h3><p><em>Cong Guo 0003, Fengchen Xue, Jingwen Leng, Yuxian Qiu <em>et al.</em></em></p><p><strong>TL;DR</strong> — Accelerates sparse deep neural network inference by restructuring sparse matrix multiplication into tiled GEMM operations that map efficiently onto GPU tensor cores.</p><p><strong>Why notable</strong> — Bridges the gap between theoretical sparsity speedups and GPU hardware realities, achieving practical inference acceleration on commodity hardware.</p><hr><h3 id=xvpfloat-risc-v-isa-extension-for-variable-extended-precision-floating-point-computation>Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation<a hidden class=anchor aria-hidden=true href=#xvpfloat-risc-v-isa-extension-for-variable-extended-precision-floating-point-computation>#</a></h3><p><em>Eric Guthmuller, César Fuguet, Andrea Bocco, Jérôme Fereyre <em>et al.</em></em></p><p><strong>TL;DR</strong> — Defines a RISC-V ISA extension supporting variable-precision floating-point operations beyond IEEE 754 standard widths, targeting HPC and scientific computing.</p><p><strong>Why notable</strong> — Addresses precision flexibility at the ISA level, enabling energy-efficient mixed-precision HPC workloads without requiring separate co-processors.</p><hr><h3 id=enabling-hw-based-task-scheduling-in-large-multicore-architectures>Enabling HW-Based Task Scheduling in Large Multicore Architectures<a hidden class=anchor aria-hidden=true href=#enabling-hw-based-task-scheduling-in-large-multicore-architectures>#</a></h3><p><em>Lucas Morais, Carlos Álvarez 0001, Daniel Jiménez-González, Juan Miguel De Haro Ruiz <em>et al.</em></em></p><p><strong>TL;DR</strong> — Implements task-scheduling logic directly in hardware for large multicore chips, reducing OS scheduling overhead and improving parallelism exploitation.</p><p><strong>Why notable</strong> — Demonstrates that offloading fine-grained task management to hardware can substantially reduce software overhead in many-core systems.</p><hr><h3 id=ara2-exploring-single--and-multi-core-vector-processing-with-an-efficient-rvv-10-compliant-open-source-processor>Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor<a hidden class=anchor aria-hidden=true href=#ara2-exploring-single--and-multi-core-vector-processing-with-an-efficient-rvv-10-compliant-open-source-processor>#</a></h3><p><em>Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli <em>et al.</em></em></p><p><strong>TL;DR</strong> — Presents Ara2, an open-source RISC-V vector processor fully compliant with RVV 1.0, evaluated across single- and multi-lane configurations for energy-efficient vector workloads.</p><p><strong>Why notable</strong> — Provides the community with a production-quality, open RVV 1.0 reference design and a thorough design-space exploration of vector-processor microarchitecture.</p><hr><h3 id=ecoflow-efficient-convolutional-dataflows-on-low-power-neural-network-accelerators>EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators<a hidden class=anchor aria-hidden=true href=#ecoflow-efficient-convolutional-dataflows-on-low-power-neural-network-accelerators>#</a></h3><p><em>Lois Orosa 0001, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos <em>et al.</em></em></p><p><strong>TL;DR</strong> — Systematically analyzes and optimizes dataflow schedules for convolutional layers on low-power DNN accelerators, yielding significant energy savings.</p><p><strong>Why notable</strong> — Provides a principled framework for dataflow selection that benefits embedded AI accelerator designers targeting energy-constrained deployments.</p><hr><h3 id=prefender-a-prefetching-defender-against-cache-side-channel-attacks-as-a-pretender>Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender<a hidden class=anchor aria-hidden=true href=#prefender-a-prefetching-defender-against-cache-side-channel-attacks-as-a-pretender>#</a></h3><p><em>Luyi Li, Jiayi Huang 0001, Lang Feng 0001, Zhongfeng Wang 0001</em></p><p><strong>TL;DR</strong> — Proposes a hardware prefetching mechanism that disguises cache access patterns to defend against conflict-based cache side-channel attacks with low performance overhead.</p><p><strong>Why notable</strong> — Addresses cache side-channel attacks at the microarchitecture level without relying on software mitigations, offering a lightweight and transparent defense.</p><hr><h3 id=randomizing-set-associative-caches-against-conflict-based-cache-side-channel-attacks>Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks<a hidden class=anchor aria-hidden=true href=#randomizing-set-associative-caches-against-conflict-based-cache-side-channel-attacks>#</a></h3><p><em>Wei Song 0002, Zihan Xue, Jinchi Han, Zhenzhen Li <em>et al.</em></em></p><p><strong>TL;DR</strong> — Introduces a cache randomization scheme for set-associative caches that eliminates conflict-based side-channel attack primitives with minimal performance overhead.</p><p><strong>Why notable</strong> — Provides a strong and low-cost architectural defense against a broad class of cache timing attacks that affect nearly all modern processors.</p><hr><h3 id=scarf-securing-chips-with-a-robust-framework-against-fabrication-time-hardware-trojans>SCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans<a hidden class=anchor aria-hidden=true href=#scarf-securing-chips-with-a-robust-framework-against-fabrication-time-hardware-trojans>#</a></h3><p><em>Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini</em></p><p><strong>TL;DR</strong> — Proposes a framework for detecting and mitigating hardware Trojans inserted during chip fabrication using lightweight logic testing combined with side-channel verification.</p><p><strong>Why notable</strong> — Tackles the increasingly critical supply-chain hardware-security threat with a practical methodology applicable during standard chip validation flows.</p><hr><h3 id=grande-efficient-near-data-processing-architecture-for-graph-neural-networks>GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks<a hidden class=anchor aria-hidden=true href=#grande-efficient-near-data-processing-architecture-for-graph-neural-networks>#</a></h3><p><em>Sungmin Yun 0001, Hwayong Nam, Jaehyun Park 0006, Byeongho Kim <em>et al.</em></em></p><p><strong>TL;DR</strong> — Designs a near-data processing accelerator tailored for graph neural network inference, co-locating compute with graph-structured memory to cut off-chip traffic.</p><p><strong>Why notable</strong> — Demonstrates that memory-wall bottlenecks in GNN inference can be alleviated by a purpose-built PIM design, achieving substantial speedup and energy efficiency gains.</p></div><footer class=post-footer><ul class=post-tags></ul><nav class=paginav><a class=prev href=https://pub.sqrt.fr/vincent/publish-assistant/cloud-edge/digests/sec-2024/><span class=title>« Prev</span>
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