venue: TC year: 2025 selected: - title: "RV-CURE: A RISC-V Capability Architecture for Full Memory Safety" authors: - Yonghae Kim - Anurag Kar - Jaewon Lee - Jaekyu Lee - Hyesoon Kim tldr: "Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack." why_notable: "Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems." - title: "DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation" authors: - Haitao Du - Yuxuan Yang 0009 - Song Chen 0001 - Yi Kang tldr: "Proposes an in-DRAM cache that isolates frequently accessed rows, preventing RowHammer hammering without costly refresh storms or off-chip overhead." why_notable: "Addresses the escalating RowHammer threat directly inside DRAM with negligible performance overhead, making it a compelling candidate for near-term hardware adoption." - title: "SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation" authors: - Wontak Han - Hyunjun Cho - Donghyuk Kim - Joo-Young Kim 0001 tldr: "Implements subarray-level PIM with lookup-table interpolation inside DRAM to accelerate the memory-bound non-linear operations of transformer inference." why_notable: "Shows how fine-grained PIM design can unblock the bottlenecks specific to LLM inference, providing a pathway to in-memory acceleration of attention and activation layers." - title: "FlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization" authors: - Guohao Dai 0001 - Ke Hong - Qiuli Mao - Xiuhong Li - Jiaming Xu - Haofeng Huang - Hongtu Xia - Xuefei Ning - Shengen Yan - Yun Liang 0001 - Yu Wang 0002 tldr: "Extends FlashDecoding with memory and latency optimizations to significantly raise GPU throughput during the autoregressive generation phase of large language models." why_notable: "Directly advances the state of the art in LLM serving efficiency on GPU clusters, a problem with immediate commercial relevance." - title: "Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation" authors: - Jordi Fornt - Enrico Reggiani - Pau Fontova-Musté - Narcís Rodas - Alessandro Pappalardo - Osman Sabri Unsal - Adrián Cristal Kestelman - Josep Altet - Francesc Moll - Jaume Abella 0001 tldr: "Adds lightweight ISA extensions to a RISC-V CPU for mixed-precision inference via binary segmentation, avoiding heavyweight SIMD or dedicated accelerators." why_notable: "Provides a cost-effective route to on-device DNN inference on RISC-V embedded cores without the area overhead of a full vector or matrix unit." - title: "Optimizing Tiny Transformers on Low-Power MCUs" authors: - Victor Jean-Baptiste Jung - Alessio Burrello - Moritz Scherer 0001 - Francesco Conti 0001 - Luca Benini tldr: "Develops an automated deployment pipeline for transformer models on microcontrollers, exploiting tiling, quantization, and kernel fusion to fit within tight memory and compute budgets." why_notable: "Enables state-of-the-art sequence models to run on ultra-low-power embedded processors, bridging the gap between transformer research and IoT hardware constraints." - title: "Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design" authors: - Jinyi Deng - Xinru Tang - Jiahao Zhang - Yuxuan Li - Linyun Zhang - Fengbin Tu - Shaojun Wei - Yang Hu 0001 - Shouyi Yin tldr: "Systematically studies control-flow support in dataflow/spatial accelerators and proposes a general control-flow plane abstraction that unifies existing ad hoc designs." why_notable: "Offers a principled framework for architects designing the next generation of programmable spatial accelerators, where irregular control flow remains a fundamental challenge." - title: "High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT" authors: - Yijun Cui - Junjie Zhong - Bei Wang 0013 - Tianyu Xu 0002 - Chenghua Wang - Weiqiang Liu 0001 tldr: "Presents an optimized ASIC accelerator for CRYSTALS-Dilithium digital signatures using an improved multi-delay commutator NTT to maximize throughput." why_notable: "Delivers high-performance hardware for a NIST-standardized post-quantum signature scheme, essential for quantum-safe authentication in future systems." - title: "Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping" authors: - Yingxue Gao - Teng Wang - Lei Gong 0003 - Chao Wang 0003 - Dong Dai 0001 - Yang Yang 0080 - Xianglan Chen - Xi Li 0003 - Xuehai Zhou tldr: "Designs a heterogeneous accelerator for Vision Transformers that adaptively maps attention and FFN computations onto specialized dataflow engines to maximize utilization." why_notable: "Addresses the heterogeneous computational demands of ViT workloads with a flexible architecture, demonstrating state-of-the-art throughput-per-watt on image recognition tasks." - title: "29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer" authors: - Xun Wang 0010 - Xiangyu Meng 0005 - Zhuoqiang Guo - Mingzhen Li 0001 - Lijun Liu - Mingfan Li - Qian Xiao - Tong Zhao - Ninghui Sun - Guangming Tan - Weile Jia tldr: "Scales a machine-learning-based molecular dynamics simulation to 29 billion atoms at ab-initio accuracy across 35 million cores on the Sunway supercomputer." why_notable: "Sets a landmark in scientific HPC scalability, demonstrating how deep co-design of architecture, communication, and ML models enables quantum-accurate simulation at unprecedented scale." - title: "AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems" authors: - Thomas Benz - Alessandro Ottaviano - Chaoqun Liang - Robert Balas - Angelo Garofalo - Francesco Restuccia 0002 - Alessandro Biondi 0001 - Davide Rossi 0001 - Luca Benini tldr: "Introduces an open-source AXI interconnect module that enforces bandwidth and latency isolation between mixed-criticality components in heterogeneous SoCs." why_notable: "Provides a practical, standards-compliant hardware mechanism for achieving real-time guarantees in safety-critical SoCs built from commodity IP blocks." - title: "Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators" authors: - Arne Symons - Linyan Mei - Steven Colleman - Pouya Houshmand - Sebastian Karl - Marian Verhelst tldr: "Presents a framework for exploring the design space of layer-fused DNN execution across heterogeneous arrays, jointly optimizing tiling, scheduling, and memory allocation." why_notable: "Enables systematic co-design of DNN models and heterogeneous accelerators, a key capability as networks grow more complex and hardware resources more diverse."