content updates, various fixes
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khannurien
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site/data/papers/TC-2024-digest.yaml
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site/data/papers/TC-2024-digest.yaml
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venue: TC
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year: 2024
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selected:
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- title: "Achieving DRAM-Like PCM by Trading Off Capacity for Latency"
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authors:
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- Irina Alam
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- Puneet Gupta 0001
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tldr: "Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes."
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why_notable: "Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems."
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- title: "A High-Performance, Energy-Efficient Modular DMA Engine Architecture"
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authors:
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- Thomas Benz
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- Michael Rogenmoser
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- Paul Scheffler
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- Samuel Riedel
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- Alessandro Ottaviano
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- Andreas Kurth
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- Torsten Hoefler
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- Luca Benini
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tldr: "Presents a modular, parametric DMA engine design achieving high bandwidth and low energy overhead for heterogeneous SoC data movement."
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why_notable: "Provides an open, well-evaluated DMA baseline that researchers building custom SoCs or accelerators can directly reuse or benchmark against."
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- title: "Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber"
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authors:
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- Wenbo Guo 0009
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- Shuguo Li
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tldr: "Designs a compact FPGA/ASIC hardware accelerator for the CRYSTALS-Kyber post-quantum key encapsulation mechanism using a split-radix NTT."
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why_notable: "Demonstrates efficient hardware realization of a NIST-standardized post-quantum algorithm, critical for transitioning real systems to quantum-resistant cryptography."
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- title: "Accelerating Sparse DNNs Based on Tiled GEMM"
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authors:
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- Cong Guo 0003
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- Fengchen Xue
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- Jingwen Leng
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- Yuxian Qiu
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- Yue Guan 0003
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- Weihao Cui
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- Quan Chen 0002
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- Minyi Guo
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tldr: "Accelerates sparse deep neural network inference by restructuring sparse matrix multiplication into tiled GEMM operations that map efficiently onto GPU tensor cores."
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why_notable: "Bridges the gap between theoretical sparsity speedups and GPU hardware realities, achieving practical inference acceleration on commodity hardware."
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- title: "Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation"
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authors:
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- Eric Guthmuller
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- César Fuguet
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- Andrea Bocco
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- Jérôme Fereyre
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- Riccardo Alidori
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- Ihsane Tahir
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- Yves Durand
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tldr: "Defines a RISC-V ISA extension supporting variable-precision floating-point operations beyond IEEE 754 standard widths, targeting HPC and scientific computing."
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why_notable: "Addresses precision flexibility at the ISA level, enabling energy-efficient mixed-precision HPC workloads without requiring separate co-processors."
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- title: "Enabling HW-Based Task Scheduling in Large Multicore Architectures"
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authors:
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- Lucas Morais
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- Carlos Álvarez 0001
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- Daniel Jiménez-González
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- Juan Miguel De Haro Ruiz
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- Guido Araujo
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- Michael Frank 0008
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- Alfredo Goldman
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- Xavier Martorell
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tldr: "Implements task-scheduling logic directly in hardware for large multicore chips, reducing OS scheduling overhead and improving parallelism exploitation."
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why_notable: "Demonstrates that offloading fine-grained task management to hardware can substantially reduce software overhead in many-core systems."
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- title: "Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor"
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authors:
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- Matteo Perotti
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- Matheus A. Cavalcante
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- Renzo Andri
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- Lukas Cavigelli
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- Luca Benini
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tldr: "Presents Ara2, an open-source RISC-V vector processor fully compliant with RVV 1.0, evaluated across single- and multi-lane configurations for energy-efficient vector workloads."
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why_notable: "Provides the community with a production-quality, open RVV 1.0 reference design and a thorough design-space exploration of vector-processor microarchitecture."
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- title: "EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators"
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authors:
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- Lois Orosa 0001
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- Skanda Koppula
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- Yaman Umuroglu
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- Konstantinos Kanellopoulos
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- Juan Gómez-Luna
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- Michaela Blott
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- Kees A. Vissers
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- Onur Mutlu
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tldr: "Systematically analyzes and optimizes dataflow schedules for convolutional layers on low-power DNN accelerators, yielding significant energy savings."
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why_notable: "Provides a principled framework for dataflow selection that benefits embedded AI accelerator designers targeting energy-constrained deployments."
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- title: "Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender"
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authors:
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- Luyi Li
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- Jiayi Huang 0001
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- Lang Feng 0001
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- Zhongfeng Wang 0001
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tldr: "Proposes a hardware prefetching mechanism that disguises cache access patterns to defend against conflict-based cache side-channel attacks with low performance overhead."
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why_notable: "Addresses cache side-channel attacks at the microarchitecture level without relying on software mitigations, offering a lightweight and transparent defense."
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- title: "Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks"
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authors:
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- Wei Song 0002
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- Zihan Xue
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- Jinchi Han
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- Zhenzhen Li
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- Peng Liu 0005
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tldr: "Introduces a cache randomization scheme for set-associative caches that eliminates conflict-based side-channel attack primitives with minimal performance overhead."
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why_notable: "Provides a strong and low-cost architectural defense against a broad class of cache timing attacks that affect nearly all modern processors."
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- title: "SCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans"
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authors:
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- Mohammad Eslami
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- Tara Ghasempouri
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- Samuel Pagliarini
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tldr: "Proposes a framework for detecting and mitigating hardware Trojans inserted during chip fabrication using lightweight logic testing combined with side-channel verification."
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why_notable: "Tackles the increasingly critical supply-chain hardware-security threat with a practical methodology applicable during standard chip validation flows."
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- title: "GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks"
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authors:
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- Sungmin Yun 0001
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- Hwayong Nam
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- Jaehyun Park 0006
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- Byeongho Kim
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- Jung Ho Ahn
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- Eojin Lee
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tldr: "Designs a near-data processing accelerator tailored for graph neural network inference, co-locating compute with graph-structured memory to cut off-chip traffic."
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why_notable: "Demonstrates that memory-wall bottlenecks in GNN inference can be alleviated by a purpose-built PIM design, achieving substantial speedup and energy efficiency gains."
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