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site/content/digests/TC-2025/index.md

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+---
+title: TC 2025 Digest
+venue: TC
+year: 2025
+date: '2025-01-01'
+tags: []
+paper_count: 12
+draft: false
+---
+
+12 papers selected.
+
+---
+
+### RV-CURE: A RISC-V Capability Architecture for Full Memory Safety
+
+*Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee *et al.**
+
+**TL;DR** — Extends the RISC-V ISA with hardware capabilities to enforce full memory safety—including bounds checking and pointer provenance—across the entire software stack.
+
+**Why notable** — Demonstrates that capability-based memory safety can be integrated into an open ISA at low cost, with implications for deploying safe-by-default embedded and server systems.
+
+---
+
+### DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation
+
+*Haitao Du, Yuxuan Yang 0009, Song Chen 0001, Yi Kang*
+
+**TL;DR** — Proposes an in-DRAM cache that isolates frequently accessed rows, preventing RowHammer hammering without costly refresh storms or off-chip overhead.
+
+**Why notable** — Addresses the escalating RowHammer threat directly inside DRAM with negligible performance overhead, making it a compelling candidate for near-term hardware adoption.
+
+---
+
+### SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation
+
+*Wontak Han, Hyunjun Cho, Donghyuk Kim, Joo-Young Kim 0001*
+
+**TL;DR** — Implements subarray-level PIM with lookup-table interpolation inside DRAM to accelerate the memory-bound non-linear operations of transformer inference.
+
+**Why notable** — Shows how fine-grained PIM design can unblock the bottlenecks specific to LLM inference, providing a pathway to in-memory acceleration of attention and activation layers.
+
+---
+
+### FlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization
+
+*Guohao Dai 0001, Ke Hong, Qiuli Mao, Xiuhong Li *et al.**
+
+**TL;DR** — Extends FlashDecoding with memory and latency optimizations to significantly raise GPU throughput during the autoregressive generation phase of large language models.
+
+**Why notable** — Directly advances the state of the art in LLM serving efficiency on GPU clusters, a problem with immediate commercial relevance.
+
+---
+
+### Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation
+
+*Jordi Fornt, Enrico Reggiani, Pau Fontova-Musté, Narcís Rodas *et al.**
+
+**TL;DR** — Adds lightweight ISA extensions to a RISC-V CPU for mixed-precision inference via binary segmentation, avoiding heavyweight SIMD or dedicated accelerators.
+
+**Why notable** — Provides a cost-effective route to on-device DNN inference on RISC-V embedded cores without the area overhead of a full vector or matrix unit.
+
+---
+
+### Optimizing Tiny Transformers on Low-Power MCUs
+
+*Victor Jean-Baptiste Jung, Alessio Burrello, Moritz Scherer 0001, Francesco Conti 0001 *et al.**
+
+**TL;DR** — Develops an automated deployment pipeline for transformer models on microcontrollers, exploiting tiling, quantization, and kernel fusion to fit within tight memory and compute budgets.
+
+**Why notable** — Enables state-of-the-art sequence models to run on ultra-low-power embedded processors, bridging the gap between transformer research and IoT hardware constraints.
+
+---
+
+### Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design
+
+*Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li *et al.**
+
+**TL;DR** — Systematically studies control-flow support in dataflow/spatial accelerators and proposes a general control-flow plane abstraction that unifies existing ad hoc designs.
+
+**Why notable** — Offers a principled framework for architects designing the next generation of programmable spatial accelerators, where irregular control flow remains a fundamental challenge.
+
+---
+
+### High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
+
+*Yijun Cui, Junjie Zhong, Bei Wang 0013, Tianyu Xu 0002 *et al.**
+
+**TL;DR** — Presents an optimized ASIC accelerator for CRYSTALS-Dilithium digital signatures using an improved multi-delay commutator NTT to maximize throughput.
+
+**Why notable** — Delivers high-performance hardware for a NIST-standardized post-quantum signature scheme, essential for quantum-safe authentication in future systems.
+
+---
+
+### Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping
+
+*Yingxue Gao, Teng Wang, Lei Gong 0003, Chao Wang 0003 *et al.**
+
+**TL;DR** — Designs a heterogeneous accelerator for Vision Transformers that adaptively maps attention and FFN computations onto specialized dataflow engines to maximize utilization.
+
+**Why notable** — Addresses the heterogeneous computational demands of ViT workloads with a flexible architecture, demonstrating state-of-the-art throughput-per-watt on image recognition tasks.
+
+---
+
+### 29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer
+
+*Xun Wang 0010, Xiangyu Meng 0005, Zhuoqiang Guo, Mingzhen Li 0001 *et al.**
+
+**TL;DR** — Scales a machine-learning-based molecular dynamics simulation to 29 billion atoms at ab-initio accuracy across 35 million cores on the Sunway supercomputer.
+
+**Why notable** — Sets a landmark in scientific HPC scalability, demonstrating how deep co-design of architecture, communication, and ML models enables quantum-accurate simulation at unprecedented scale.
+
+---
+
+### AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
+
+*Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas *et al.**
+
+**TL;DR** — Introduces an open-source AXI interconnect module that enforces bandwidth and latency isolation between mixed-criticality components in heterogeneous SoCs.
+
+**Why notable** — Provides a practical, standards-compliant hardware mechanism for achieving real-time guarantees in safety-critical SoCs built from commodity IP blocks.
+
+---
+
+### Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
+
+*Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand *et al.**
+
+**TL;DR** — Presents a framework for exploring the design space of layer-fused DNN execution across heterogeneous arrays, jointly optimizing tiling, scheduling, and memory allocation.
+
+**Why notable** — Enables systematic co-design of DNN models and heterogeneous accelerators, a key capability as networks grow more complex and hardware resources more diverse.
+