12 papers selected.
Achieving DRAM-Like PCM by Trading Off Capacity for Latency
Irina Alam, Puneet Gupta 0001
TL;DR — Proposes a capacity-for-latency trade-off in Phase Change Memory to match DRAM-level access latency without specialized process changes.
Why notable — Offers a practical path to deploying PCM as a DRAM alternative, directly addressing the latency gap that has blocked PCM adoption in main-memory systems.
A High-Performance, Energy-Efficient Modular DMA Engine Architecture
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel et al.
TL;DR — Presents a modular, parametric DMA engine design achieving high bandwidth and low energy overhead for heterogeneous SoC data movement.
Why notable — Provides an open, well-evaluated DMA baseline that researchers building custom SoCs or accelerators can directly reuse or benchmark against.
Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber
Wenbo Guo 0009, Shuguo Li
TL;DR — Designs a compact FPGA/ASIC hardware accelerator for the CRYSTALS-Kyber post-quantum key encapsulation mechanism using a split-radix NTT.
Why notable — Demonstrates efficient hardware realization of a NIST-standardized post-quantum algorithm, critical for transitioning real systems to quantum-resistant cryptography.
Accelerating Sparse DNNs Based on Tiled GEMM
Cong Guo 0003, Fengchen Xue, Jingwen Leng, Yuxian Qiu et al.
TL;DR — Accelerates sparse deep neural network inference by restructuring sparse matrix multiplication into tiled GEMM operations that map efficiently onto GPU tensor cores.
Why notable — Bridges the gap between theoretical sparsity speedups and GPU hardware realities, achieving practical inference acceleration on commodity hardware.
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation
Eric Guthmuller, César Fuguet, Andrea Bocco, Jérôme Fereyre et al.
TL;DR — Defines a RISC-V ISA extension supporting variable-precision floating-point operations beyond IEEE 754 standard widths, targeting HPC and scientific computing.
Why notable — Addresses precision flexibility at the ISA level, enabling energy-efficient mixed-precision HPC workloads without requiring separate co-processors.
Enabling HW-Based Task Scheduling in Large Multicore Architectures
Lucas Morais, Carlos Álvarez 0001, Daniel Jiménez-González, Juan Miguel De Haro Ruiz et al.
TL;DR — Implements task-scheduling logic directly in hardware for large multicore chips, reducing OS scheduling overhead and improving parallelism exploitation.
Why notable — Demonstrates that offloading fine-grained task management to hardware can substantially reduce software overhead in many-core systems.
Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor
Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli et al.
TL;DR — Presents Ara2, an open-source RISC-V vector processor fully compliant with RVV 1.0, evaluated across single- and multi-lane configurations for energy-efficient vector workloads.
Why notable — Provides the community with a production-quality, open RVV 1.0 reference design and a thorough design-space exploration of vector-processor microarchitecture.
EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators
Lois Orosa 0001, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos et al.
TL;DR — Systematically analyzes and optimizes dataflow schedules for convolutional layers on low-power DNN accelerators, yielding significant energy savings.
Why notable — Provides a principled framework for dataflow selection that benefits embedded AI accelerator designers targeting energy-constrained deployments.
Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender
Luyi Li, Jiayi Huang 0001, Lang Feng 0001, Zhongfeng Wang 0001
TL;DR — Proposes a hardware prefetching mechanism that disguises cache access patterns to defend against conflict-based cache side-channel attacks with low performance overhead.
Why notable — Addresses cache side-channel attacks at the microarchitecture level without relying on software mitigations, offering a lightweight and transparent defense.
Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks
Wei Song 0002, Zihan Xue, Jinchi Han, Zhenzhen Li et al.
TL;DR — Introduces a cache randomization scheme for set-associative caches that eliminates conflict-based side-channel attack primitives with minimal performance overhead.
Why notable — Provides a strong and low-cost architectural defense against a broad class of cache timing attacks that affect nearly all modern processors.
SCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans
Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini
TL;DR — Proposes a framework for detecting and mitigating hardware Trojans inserted during chip fabrication using lightweight logic testing combined with side-channel verification.
Why notable — Tackles the increasingly critical supply-chain hardware-security threat with a practical methodology applicable during standard chip validation flows.
GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks
Sungmin Yun 0001, Hwayong Nam, Jaehyun Park 0006, Byeongho Kim et al.
TL;DR — Designs a near-data processing accelerator tailored for graph neural network inference, co-locating compute with graph-structured memory to cut off-chip traffic.
Why notable — Demonstrates that memory-wall bottlenecks in GNN inference can be alleviated by a purpose-built PIM design, achieving substantial speedup and energy efficiency gains.